For most of the last decade, “edge AI” meant one of two things: either a high-end inference platform like NVIDIA Jetson costing hundreds of pounds, or TinyML on a microcontroller that could classify a handful of audio patterns but not much else. There wasn’t a lot in between. That gap is closing fast in 2026, and the driver is a new generation of IoT system-on-chips that include dedicated neural processing units as a standard feature rather than a premium add-on.
The shift was visible at Computex 2026, where chipmakers queued up to announce SoCs with embedded AI accelerators targeting price points well below what’s been typical for this class of hardware. MediaTek, Espressif, NXP, and several Chinese fabless companies all showed IoT chips with NPUs delivering between 1 and 8 TOPS (tera-operations per second) — a range that sounds modest next to NVIDIA’s 275 TOPS on the Jetson AGX Orin, but is more than sufficient for the inference tasks most IoT devices actually need to run.
What 1–4 TOPS Actually Gets You
The use cases that fit within the capability of lightweight NPUs are more useful than the raw numbers suggest. Anomaly detection on sensor data — identifying when a machine’s vibration pattern changes in a way that indicates bearing wear — runs comfortably on sub-1-TOPS hardware with the right model. Audio keyword detection, wake-word recognition, and basic acoustic anomaly identification are well within range. Image classification at low resolution (is there a person in this frame? is this product defect type A or type B?) runs fine with quantised MobileNet-class models on 2–4 TOPS silicon.
What you can’t do on this class of hardware is run large vision transformers, process high-resolution video streams in real time, or do anything that requires multi-step reasoning. Those tasks still belong further up the edge hierarchy — on Jetson-class or Dragonwing-class hardware, or in the cloud. The point of the lightweight NPU tier isn’t to replace those platforms; it’s to push a subset of genuinely useful inference work down to devices that have historically just been dumb data collectors.
The SoCs Worth Watching
Espressif’s ESP32-P4, which began shipping in volume in late 2025, includes a vector extension that accelerates neural network inference significantly compared to its predecessors. It’s not a dedicated NPU in the strict sense, but the performance-per-watt on small quantised models is good enough that the distinction matters less than it sounds. The ESP32 ecosystem’s enormous developer community means firmware frameworks, model conversion tools, and community support are all substantially further along than competitors.
NXP’s i.MX 93 family has a more conventional 0.5-TOPS NPU alongside the application processor, positioned at smart home, industrial sensing, and audio processing applications. The integration with NXP’s eIQ machine learning toolkit and their MCUXpresso development environment makes it reasonably accessible for embedded engineers without a deep ML background.
On the higher end of this tier, Rockchip’s RV1106 offers around 1 TOPS and has found a home in smart cameras, access control, and industrial vision applications at price points that undercut more capable alternatives significantly. It’s particularly popular in Asian OEM products, which means it shows up across a wide range of end devices whether or not the product documentation mentions it.
What Changes About Edge Architecture
The practical implication of NPUs arriving in mass-market SoCs is that the classic edge architecture — dumb endpoint, smart gateway, cloud processing — needs revisiting. If the endpoint itself can do useful inference, then the gateway’s role shifts from raw computation to aggregation, routing, and managing the connection to cloud analytics. Some tasks that currently generate constant upstream traffic — sending every sensor reading to a cloud ML model for classification — can be handled locally, with only the classified result or an exception transmitted.
This has genuine benefits beyond latency. Data minimisation is increasingly a regulatory consideration; under GDPR and the UK Data Protection Act, processing personal data locally (and only transmitting non-identifiable inference results) is a cleaner architecture from a compliance standpoint. It also reduces cloud costs and, in battery-powered deployments, the energy cost of radio transmission — which is often higher than the inference computation itself.
The challenge is that this architectural shift requires rethinking how models are developed and deployed. A model trained in TensorFlow and running on a cloud GPU doesn’t arrive at a 2 TOPS NPU ready to use. It needs to be quantised, optimised, and validated on the target hardware — and then redeployed when you update it. The tooling for this is improving quickly (TensorFlow Lite, ONNX Runtime, ExecuTorch, and vendor-specific tools like NXP’s eIQ all address parts of this), but it’s still meaningfully more involved than cloud-side model management.
Where This Is Landing First
Predictive maintenance in manufacturing is probably the fastest-growing deployment category for this class of hardware in 2026. Vibration sensors, temperature sensors, and acoustic sensors on factory equipment can now do first-pass anomaly detection locally, alerting the maintenance system only when a threshold is crossed rather than streaming raw data continuously. The ROI case is well understood, the models required are relatively simple, and the hardware cost has dropped to a point where it makes sense to instrument individual machines rather than sampled populations.
Smart buildings are another early deployment area, particularly for occupancy sensing and HVAC optimisation. The ability to do person-detection inference locally (without transmitting images) addresses the privacy objections that have slowed adoption of camera-based occupancy sensing in workplaces — a meaningful blocker in the UK specifically, given ICO guidance on workplace surveillance.
The trajectory here is pretty clear. NPUs in IoT SoCs are following the same curve as GPS, Bluetooth, and cellular connectivity before them — an initially premium feature that becomes standard hardware within a few generations. The interesting work right now is in the tooling, deployment pipelines, and architectural patterns that let development teams actually take advantage of the capability.