For most of the past decade, edge AI hardware meant Arm. Cortex-M for microcontrollers, Cortex-A for more capable devices, with MIPS holding on in legacy industrial systems. RISC-V got attention in research and among hobbyists, but it wasn’t a serious option for production deployments.

That’s changed in the past 18 months. RISC-V is now appearing in production edge AI chips — and more importantly, it’s appearing with dedicated neural processing units (NPUs) alongside the general-purpose cores. For teams choosing an inference platform, the choice is no longer purely Arm.

What’s actually driving the shift

The short version: RISC-V’s open ISA eliminates licensing fees, and as edge AI silicon becomes more specialised, the ability to customise the instruction set without paying royalties to a third party is genuinely valuable.

When you’re designing a chip for a specific edge inference task — say, anomaly detection in a motor controller, or keyword spotting in an industrial sensor — the standard general-purpose instruction set matters less than the efficiency of the AI accelerator alongside it. RISC-V lets silicon designers add custom extensions for their specific workloads without worrying about ISA licensing constraints. For chips shipping in volume across industrial deployments, that adds up.

The result is a growing catalogue of edge AI chips with RISC-V cores and purpose-built NPUs. MIPS’s S8200 series uses RISC-V alongside a dedicated AI accelerator for vision and audio edge inference. Nordic Semiconductor’s nRF54LM20B — announced earlier this year — pairs a RISC-V core with what they’re calling the Axon NPU, targeting ultra-low-power ML inference in IoT devices. The trend is clearly accelerating: the edge NPU market is projected to grow at over 73% annually through 2028, and RISC-V is claiming a significant share of new designs.

What NPUs actually do at the edge

An NPU — neural processing unit — is dedicated silicon for running neural network inference efficiently. It’s not a GPU (too power-hungry for most edge applications) and it’s not just a fast CPU. It’s an accelerator designed specifically to execute the matrix multiplications and activations that make up most inference workloads, with much better performance-per-watt than general-purpose cores.

For edge AI, that matters enormously. A typical edge device running inference on a CPU might burn 200–500mW. The same model on an NPU might use 5–20mW. On a battery-powered sensor or an embedded industrial device, that difference determines whether the device is viable at all.

The models running on these NPUs are quantised, compressed versions of larger models — INT8 or INT4 precision rather than the FP32 you’d use in training. This isn’t a compromise you make grudgingly; the accuracy loss is minimal for most practical inference tasks, and the efficiency gains are substantial.

What this means for edge AI developers

The practical change is toolchain maturity. Running TensorFlow Lite or ONNX Runtime on a RISC-V NPU used to mean significant porting work. That’s improved substantially. TFLite Micro now has RISC-V backend support. ONNX Runtime has begun shipping prebuilt binaries for common RISC-V configurations. The ecosystems that developers are already familiar with are starting to treat RISC-V as a first-class target rather than an afterthought.

Cross-platform model optimisation is also getting easier. Tools like IREE (Intermediate Representation Execution Environment) let you compile a model once and deploy it across different accelerator backends — including RISC-V NPUs — without rewriting the inference pipeline. For teams that need to target multiple edge hardware configurations, this is genuinely useful.

That said, the toolchain is still maturing. You’ll encounter gaps, particularly for newer chips where vendor SDK support hasn’t fully caught up with the hardware capabilities. The debugging experience is rougher than it is on well-established Arm platforms. And the community of developers with hands-on RISC-V NPU experience is still much smaller than the Arm equivalent.

Where RISC-V edge AI makes most sense right now

It’s not the right call for every project. If you’re targeting consumer devices, deploying on mainstream embedded platforms, or if your team has deep Arm expertise and limited time for toolchain experimentation, sticking with Arm Cortex-based hardware is still the pragmatic choice.

Where RISC-V NPUs start to look compelling:

  • High-volume industrial production where licensing costs accumulate meaningfully across a fleet of devices
  • Highly specialised applications where you want to customise the execution pipeline and aren’t constrained by off-the-shelf toolchains
  • New product designs that can afford to start with RISC-V now and benefit from the ecosystem as it matures
  • Power-constrained IoT where the specific NPU characteristics of a new RISC-V chip are measurably better than the Arm alternatives

The trajectory is clear. RISC-V is no longer just a research architecture. It’s in production hardware that’s shipping today, and the edge AI ecosystem around it is building out at a meaningful pace. Whether it displaces Arm for mainstream edge workloads over the next few years is still an open question, but the gap is closing faster than it was a year ago.